Attendant on the miniaturization of semiconductor devices on a design rule basis, there has been a general tendency in the wiring process toward a shift of the wiring material from aluminum (Al) to copper (Cu) and toward the application of a lower dielectric constant material to the inter-layer insulation film. The reason for these material changes lies in that the Al wirings and the related-art inter-layer insulation film materials such as SiO2 have come to be confronted by limitations, in view of wiring delay and the like problems. While the development of semiconductor devices has been progressing with the material transitions, the modifications in material are attended by great changes in the semiconductor manufacturing process.
For example, in the case of applying Cu as a wiring material, the dry etching of wirings which has been widely used for the Al wiring generations is unsuitable to Cu, which is a material susceptible to corrosion. Therefore, where Cu is processed by dry etching in the same manner as Al, the dry etching must be carried out near critical conditions on an apparatus hardware basis, i.e., under a low pressure and a high temperature, which is unadaptable to mass production process. For the Cu wiring process at present, accordingly, there is widely used a method called the Damascene process, in which a barrier film 202 is formed on an inter-layer insulation film 201 provided with trenches or holes, then the trenches or holes are filled up with Cu 203, and the Cu portions not contributing to wiring (field portions) are removed by CMP (Chemical Mechanical Polishing).
The CMP technology is a comparatively well-established technology the application of which started with the 0.5 μm design rule, at the earliest. In the beginning stage of application of the CMP technology, the material to be polished is the inter-layer insulation film. In the CMP technology, however, there are pattern dependency problems, such as different polishing rates in different wiring density areas; particularly, the phenomenon called “erosion” in which polishing is accelerated in denser wiring areas has been a great problem to be solved. These problems have been technically improved to a level satisfactory for application to mass production, through improvements in CMP hardware and improvements of CMP consumables such as slurry and pad. These improvements are owing to the material of the inter-layer insulation film, which is the member to be polished, particularly, the material represented by SiO2. This is because SiO2 constituting the member to be polished is a comparatively hard material, accompanied by comparatively high degrees of freedom as to CMP parameters.
However, the material to be polished by the Damascene process is Cu, which is a metallic material being soft and viscous, as compared with SiO2. In addition, Cu is susceptible to reaction with an acid or alkali contained in the slurry. Due to such properties of Cu, the Cu wiring process using CMP involves the following problems.
(1) Erosion
As has been the problem in the CMP of the inter-layer insulation film (oxide film), in the areas of higher wiring density patterns, the polishing of different materials differing in polishing rate leads to the problem that a local pressure is exerted on the lower polishing rate portions as the higher polishing rate portions are polished, and the synergistic effect increases the difference in polishing rate. As a result, a scooped-out shape is formed in the area of a higher wiring density pattern, as shown in FIG. 19.
(2) Dishing
Dishing is a phenomenon in which a broad wiring portion having a width of 30 μm or more is polished in an accelerated manner, and the resulting wiring has a recessed shape as shown in FIG. 20. The dishing progresses acceleratedly according to an increase in the polishing pressure and a deformation of the polishing pad. For suppressing the dishing, it is effective to polish under a lower load. The lowering of the load, however, leads to a lowered polishing rate, rendering the polishing unadaptable to mass production process.
(3) Wiring (Cu) Recess
The wiring (Cu) recess means the condition where wiring trenches or holes formed in the inter-layer insulation film are not filled with Cu (the material for forming the wirings) up to the height of the inter-layer insulation film, as shown in FIG. 21. Therefore, the above-mentioned erosion and dishing are also kinds of recess. While the erosion and the dishing are principally and greatly dependent on the polishing pressure, chemical etching by an acid or alkali constituting the slurry is an additional cause of the recessing (etching) of Cu. Since an increase in the polishing pressure leads to the progress of erosion and/or dishing as above-mentioned, it is necessary, in application of CMP to mass production process, to investigate an enhancement of chemical reaction rate for the purpose of raising the polishing rate. This approach, however, would lead to recess formation through etching of Cu due to a chemical attack.
(4) Delamination of Inter-Layer Insulation Film
As a countermeasure against the wiring delay, not only the lowering in the resistance of the wirings but also a reduction in the capacitance of the inter-layer insulation film may be mentioned, and a specific method for reducing the capacitance resides in applying a low dielectric constant material to the inter-layer insulation film. The lowering in the dielectric constant of the inter-layer insulation film is generally contrived by forming the film from a porous material, but the use of a porous material is attended by an increase in fragility, leading to a degradation in mechanical strength. Then, the use of a porous material has the bad effect that the low dielectric constant material of the inter-layer insulation film may be delaminated under the pressure exerted in the Cu CMP, as shown in FIG. 22.
In this way, the formation of Cu wirings by the Damascene process involves the problems of reduction in film thickness of wiring portions and degradation in planarization, due to erosion, dishing, recess and the like. The reduction in film thickness of wiring portions causes a current density over the designed value to be supplied on the wirings, leading to, for example, a lowered electromigration (EM) resistance and, hence, to a great damage to the reliability of the wiring.
On the other hand, a shape including a non-planarity such as erosion induces pattern formation defects. Then, in the lithography step, an increase in absolute steps lowers the DOF (Depth of Focus) and, therefore, it is impossible to form the desired pattern. This tendency becomes conspicuous particularly in more miniaturized patterns. Besides, the absolute steps are more emphasized attendant on an increase in the number of wiring layers. For example, in the case of a layout in which the step portions are stacked, the recessing is augmented by the step amount, whereby the absolute steps are enlarged. The increase of the step corresponds to a trench portion in the inter-layer insulation film, so that Cu will remain in the stepped portion upon the Cu CMP, resulting in a fatal defect of shortcircuit in the semiconductor device, as shown in FIG. 23.
In addition, the application of the low dielectric constant material to the inter-layer insulation film involves the problem that, since the low dielectric constant material is a fragile material, as above-mentioned, the low dielectric constant material is delaminated under the pressure or load exerted in the CMP, resulting in a fatal damage.
Meanwhile, a Cu polishing method in which electropolishing is conducted under a low-pressure or pressure-free condition has recently been developed as a polishing and planarizing method compatible with the use of a low dielectric constant material. This technology is characterized in that the surface of Cu constituting the film to be polished is converted, by application of an electrolytic voltage, into a reaction layer easy to polish or a reaction layer capable of being dissolved without polishing, and Cu is planarized. However, such a low-pressure electropolishing technology still remains, in many cases, in a hardware form situated on the extension of CMP, and low-pressure polishing on such a satisfactory level as to solve the above-mentioned problems has not yet been realized.
Thus, a technique which enables to solve the problems of shape defects such as erosion, dishing, recess, etc. and delamination of the fragile low dielectric constant material and to form Damascene wirings in favorable shape and with high reliability has not yet been established.
The present invention has been made in consideration of the above-mentioned status quo. Accordingly, it is an object of the present invention to provide a polishing method and a polishing apparatus by which excess portions of a metallic film can be removed easily and efficiently in planarizing the metallic film by polishing and which promise high-accuracy polishing. It is another object of the present invention to provide a method of manufacturing a semiconductor device by use of the polishing method and the polishing apparatus.